1. Field of the Invention
The present invention relates to a fabrication method of CMOS device, and more particularly, to a method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up.
2. Description of Related Art
A complementary MOS (CMOS) device consists of an N channel MOS (NMOS) transistor and a P channel MOS (PMOS) transistor. The drains of the NMOS transistor and of PMOS transistor are connected to each other, and the transistors selectively operate according to the voltage applied to each gate. The CMOS device has advantages of lower power consumption than a single device such as NMOS or PMOS transistor because of the small DC voltage existing between power supply terminals. Therefore, the CMOS device is applied to a low power devices as well as to high speed and high integration devices.
In the CMOS device, however, NMOS and PMOS transistor are formed on a semiconductor substrate thereby forming parasitic bipolar transistors. These parasitic bipolar transistors cause a latch-up phenomenon to occur when the CMOS device is operated, and in the worst case, latch-up results in permanent damage or operational failure.
Consequently, a BILLI (buried implanted layers for lateral isolation) structure is disclosed for the purpose of preventing the latch-up caused in the conventional CMOS device.
A method for manufacturing CMOS device with BILLI structure will be described with reference to FIGS. 1A to 1C.
As illustrated in FIG. 1A, a first mask pattern 2 is formed on a P-type semiconductor substrate 1 to expose an area where a PMOS will be later formed. A N-well impurity region 3 is then formed in the form of an island in the substrate 1 by ion-implanting using the first mask pattern 2. A punch-stop impurity region 4 for use in PMOS is formed in the form of an island in the substrate 1 wherein its depth is shallower than that of the N-well impurity region 3. A threshold voltage adjust impurity region 5 for use in PMOS is formed near the form of island in the surface of the substrate 1 wherein its depth is shallower than that of the punch stop impurity region 4 for use in PMOS.
As illustrated in FIG. 1B, a P-type buried layer 6 of a high concentration is formed in the form of an island deep in the substrate 1 by ion-implanting at a relatively high energy level. Here, the P-type buried layer 6 has portions, 6a and 6b, wherein the second portion of the P-type buried layer 6b has a step difference from the first portion 6a equal to the thickness of the first mask pattern 2, the step difference in the P-type buried layer 6 being a result of using the first mask pattern 2 during ion-implantation. The P-type buried layer 6 functions as P-well during the device's operation, and the N-well is separated from the P well, thereby preventing the latch-up in the CMOS device.
As illustrated in FIG. 1C, the first mask pattern 2 is removed. A second mask pattern 7 is then formed on the substrate 1 to expose the region where NMOS will be later formed. A punch-stop impurity region 8 and a threshold adjust impurity region 9 for use in NMOS are sequentially formed in the form of islands in the substrate 1 by ion-implanting using the second mask pattern 7. The second mask pattern 7 is then removed (not shown), and the CMOS device is manufactured with a conventional follow-up processes.
In the above-described CMOS device with BILLI structure, however, the first mask pattern 2 has a steep vertical boundary face aligned perpendicular to the substrate. There is a short coming in that the boundary face of the first mask pattern negatively affects the formation of the P-type buried layer 6 wherein during ion-implanting using the above first mask pattern 2, the P-type buried layer 6 is divided and formed separately as two separate islands as shown in FIGS. 1B & 1C, as opposed to a desired continuous formation as indicated by the dotted lines. As a result, because a continuous formation is not achieved, it is difficult to prevent the latch-up in this case.